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DATA SHEET
MOS INTEGRATED CIRCUIT
PD61P34B
4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
DESCRIPTION
The PD61P34B is a microcontroller for infrared remote control transmitters which is provided with a one-time PROM as the program memory. Because users can write programs for the PD61P34B, it is ideal for program evaluation and small-scale production of the application systems using the PD6133 or 6134. When reading this document, also refer to the PD6133, 6134 Data Sheet (U10454E).
FEATURES
* Program memory (one-time PROM) : 1002 x 10 bits * Data memory (RAM) * 9-bit programmable timer * Command execution time * Stack level * I/O pins (KI/O) * Input pins (KI) * Sense input pin (S0) * S1/LED pin (I/O) * Power supply voltage * Operating ambient temperature * Oscillator frequency * POC circuit : 32 x 4 bits : 1 channel : 16 s (when operating at fX = 500 kHz: ceramic oscillation) : 1 level (Stack RAM is for data memory RF as well.) : 8 units : 4 units : 1 unit : 1 unit (When in output mode, this is the remote control transmission display pin.) : VDD = 2.2 to 3.6 V : TA = -40 to +85 C : fX = 300 kHz to 1 MHz * Built-in carrier generation circuit for infrared remote control
APPLICATION
Infrared remote control transmitter (for AV and household electric appliances)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13595EJ2V0DS00 (2nd edition) Date Published June 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1998, 1999
PD61P34B
ORDERING INFORMATION
Part Number Package 20-pin plastic SOP (300 mil) 20-pin plastic SSOP (300 mil)
PD61P34BGS PD61P34BMC-5A4
PIN CONFIGURATION (TOP VIEW)
20-pin Plastic SOP (300 mil) * PD61P34BGS 20-pin Plastic SSOP (300 mil) * PD61P34BMC-5A4 (1) Normal operating mode
KI/O6 KI/O7 S0 S1/LED REM VDD XOUT XIN GND RESET
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0
2
Data Sheet U13595EJ2V0DS00
PD61P34B
(2) PROM programming mode
D6 D7 CLK (L)
1 2 3 4 5
20 19 18 17 16 15 14 13 12 11
D5 D4 D3 D2 D1 D0 MD3 MD2 MD1 MD0
VDD XOUT XIN GND VPP
6 7 8 9 10
Caution Round brackets ( ) indicate the pins not used in the PROM programming mode. L : Connect each of these pins to GND via a pull-down resistor.
BLOCK DIAGRAM
REM
CARRIER GENERATOR
4 CPU CORE ONETIME PROM
PORT KI
4
KI0-KI3
8
PORT KI/O
8
KI/O0-KI/O7
S1/LED
9-bit TIMER
2
PORT S
2
S0, S1/LED
RAM
RESET SYSTEM CONTROL XIN XOUT VDD GND
Data Sheet U13595EJ2V0DS00
3
PD61P34B
LIST OF FUNCTIONS
Item ROM capacity 1002 x 10 bits One-time PROM RAM capacity Stack I/O pin 32 x 4 bits 1 level (shared with RF of RAM) Key input (KI) Key I/O (KI/O) Key expansion input (S0, S1) Remote control transmitter display output (LED) Number of keys 32 keys 48 keys (when expanded by key expansion input) 96 keys (when expanded by key expansion input and diode) Clock frequency Ceramic oscillation fX = 300 to 500 kHz fX = 500 kHz to 1 MHzNote Instruction execution time Carrier frequency Timer POC circuit Supply voltage Operating ambient temperature Package 16 s (at fX = 500 kHz) fX, fX/2, fX/8, fX/12, fX/16, fX/24, no carrier (high level) 9-bit programmable timer Internal VDD = 2.2 to 3.6 V * TA = -40 to +85 C * TA = -20 to +70 C (when POC circuit used) * 20-pin plastic SOP (300 mil) * 20-pin plastic SSOP (300 mil) : 1 channel : 4 pins : 8 pins : 2 pins : 1 pin (shared with S1 pin)
PD61P34B
Note It is necessary to design the application circuit so that the RESET pin goes low at a supply voltage of less than 2.2 V.
4
Data Sheet U13595EJ2V0DS00
PD61P34B
TABLE OF CONTENTS
1. PIN FUNCTIONS .........................................................................................................................
1.1 1.2 1.3 1.4 1.5 Normal Operating Mode .................................................................................................................... PROM Programming Mode ............................................................................................................... INPUT/OUTPUT Circuits of Pins ...................................................................................................... Dealing with Unused Pins ................................................................................................................ Notes on Using KI Pin at Reset ........................................................................................................
6
6 7 8 9 9
2. DIFFERENCES AMONG PD6133, 6134, AND PD61P34B .................................................... 10
2.1 Program Memory (One-time PROM) ................................................................................................ 11
3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................. 12
3.1 3.2 3.3 Operating Mode When Writing/Verifying Program Memory .......................................................... 12 Program Memory Writing Procedure ............................................................................................... 13 Program Memory Reading Procedure ............................................................................................. 14
4. ELECTRICAL SPECIFICATIONS ............................................................................................... 15 5. CHARACTERISTIC CURVE (REFERENCE VALUES) .............................................................. 21 6. APPLIED CIRCUIT EXAMPLE ................................................................................................... 23 7. PACKAGE DRAWINGS .............................................................................................................. 24 8. RECOMMENDED SOLDERING CONDITIONS .......................................................................... 26 APPENDIX A. DEVELOPMENT TOOLS ........................................................................................ 27 APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 28
Data Sheet U13595EJ2V0DS00
5
PD61P34B
1. PIN FUNCTIONS 1.1 Normal Operating Mode
Pin No. 1 2 15-20 Symbol KI/O0-KI/O7 Function These pins refer to the 8-bit I/O ports. I/O switching can be made in 8-bit units. In INPUT mode, a pull-down resistor is added. In OUTPUT mode, they can be used as the key scan output of the key matrix. Refers to the input port. Can also be used as the key return input of the key matrix. In INPUT mode, the availability of the pull-down resistor of the S0 and S1 ports can be specified by software in terms in 2-bit units. If INPUT mode is canceled by software, this pin is placed in OFF mode and enters the high-impedance state. 4 S1/LED Refers to the I/O port. In INPUT mode (S1), this pin can also be used as the key return input of the key matrix. The availability of the pull-down resistor of the S0 and S1 ports can be specified by software in 2-bit units. In OUTPUT mode (LED), it becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs the low level from the LED output synchronously with the REM signal. Refers to the infrared remote control transmission output. The output is active high. Carrier frequency: fX, fX/8, fX/12, high-level, fX/2, fX/16, fX/24 (usable on software) Refers to the power supply. These pins are connected to system clock ceramic resonators. Refers to the ground. Normally, this pin is a system reset input. By inputting a low level, the CPU can be reset. When resetting with the POC circuit a low level is output. A pull-up resistor is incorporated. These pins refer to the 4-bit input ports. They can be used as the key return input of the key matrix. The use of the pull-down resistor can be specified by software in 4-bit units. CMOS push-pull High-level output (LED) Output Format CMOS push-pullNote 1 When Reset High-level output
3
S0
--
High-impedance (OFF mode)
5
REM
CMOS push-pull
Low-level output
6 7 8 9 10
VDD XOUT XIN GND RESET
-- -- -- --
-- Low level (oscillation stopped) -- --
11-14
KI0-KI3Note 2
--
Input (low-level)
Notes 1. Be careful about this because the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when RESET pin changes from low level to high level, or POC is released due to supply voltage startup).
6
Data Sheet U13595EJ2V0DS00
PD61P34B
1.2 PROM Programming Mode
Pin No. 1, 2 15-20 3 CLK Clock input for updating address when writing/verifying program memory 6 VDD Power Supply. Supply +6 V to this pin when writing/verifying program memory. 7 8 9 10 XOUT XIN GND VPP Clock necessary for writing program memory. Connect 500-kHz ceramic resonator to these pins. GND Supplies voltage for writing/verifying program memory. Apply +12.5 V to this pin. 11-14 MD0-MD3 Input for selecting operation mode when writing/verifying program memory. Input Input - - - - Input Symbol D0-D7 Function 8-bit data input/output when writing/verifying program memory I/O I/O
Data Sheet U13595EJ2V0DS00
7
PD61P34B
1.3 INPUT/OUTPUT Circuits of Pins
The input/output circuits of the PD61P34B pins are shown in partially simplified forms below. (1) KI/O0-KI/O7
VDD
Input buffer
(4) S0
data
Output latch
P-ch
OFF mode
output disable
Selector
N-chNote
standby release
Input buffer
pull-down flag
N-ch
N-ch
(5) S1/LED Note The drive capability is held low. (2) KI0-KI3
standby release Input buffer
VDD REM output latch
P-ch
output disable standby release Input buffer
N-ch
pull-down flag
N-ch
pull-down flag
N-ch
(3) REM
(6) RESET
VDD
VDD
P-ch
P-ch data Output latch N-ch
Carrier generator
Input buffer Internal reset signal other than POC N-ch
POC circuit
8
Data Sheet U13595EJ2V0DS00
PD61P34B
1.4 Dealing with Unused Pins
The following connections are recommended for unused pins in the normal operation mode. Table 1-1. Connections for Unused Pins
Connection Inside the microcontroller KI/O INPUT mode OUTPUT mode REM S1/LED S0 KI RESETNote -- High-level output -- OUTPUT mode (LED) setting OFF mode setting -- Built-in POC circuit Open Directly connected to GND Outside the microcontroller Open
Pin
Note If the circuit is an applied one requiring high reliability, be sure to design it in such a manner that the RESET signal is entered externally. Caution The I/O mode and the terminal output level are recommended to be fixed by setting them repeatedly in each loop of the program.
1.5 Notes on Using KI Pin at Reset
In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when RESET pin changes from low level to high level, or POC is released due to supply voltage startup).
Data Sheet U13595EJ2V0DS00
9
PD61P34B
2. DIFFERENCES AMONG PD6133, 6134, AND PD61P34B
Table 2-1 shows the differences among the PD6133, 6134, and PD61P34B. The only differences among these models are the program memory, supply voltage, system clock frequency, oscillation stabilization wait time, and POC circuit (mask option), and the CPU function and internal peripheral hardware are the same. The electrical characteristics also differ slightly. For the electrical characteristics, refer to the Data Sheet of each model. Table 2-1. Differences among PD6133, 6134, and PD61P34B (1) When POC circuit (mask option) is provided to PD6133 and 6134
Item ROM
PD61P34B
One-time PROM 1002 x 10 bits (000H to 3E9H)
PD6133
Mask ROM 512 x 10 bits (000H to 1FFH)
PD6134
1002 x 10 bits (000H to 3E9H)
Oscillation stabilization wait time * On releasing STOP mode by release condition * On releasing STOP or HALT mode by RESET input and at reset VPP pin and operating mode select pin Electrical specifications Provided Not provided 284/fX to 340/fX 60/fX to 116/fX 260/fX 36/fX
Some electrical specifications, such as data retention voltage and current consumption, differ. For details, refer to Data Sheet of each model.
(2) When POC circuit (mask option) is not provided to PD6133 and 6134
Item ROM
PD61P34B
One-time PROM 1002 x 10 bits (000H to 3E9H)
PD6133
Mask ROM 512 x 10 bits (000H to 1FFH)
PD6134
1002 x 10 bits (000H to 3E9H)
Oscillation stabilization wait time * On releasing STOP mode by release condition * On releasing STOP or HALT mode by RESET input and at reset VPP pin and operating mode select pin POC circuit Supply voltage Provided Incorporated VDD = 2.2 to 3.6 V (TA = -40 to +85 C) System clock frequency * fX = 300 to 500 kHz * fX = 500 kHz to 1MHzNote Electrical specifications * fX = 300 to 500 kHz * fX = 300 kHz to 1 MHz (VDD = 2.2 to 3.6 V) Not provided Not provided VDD = 1.8 to 3.6 V (TA = -40 to +85 C) 284/fX to 340/fX 60/fX to 116/fX 260/fX 36/fX
Some electrical specifications, such as data retention voltage and current consumption, differ. For details, refer to Data Sheet of each model.
Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.2 V.
10
Data Sheet U13595EJ2V0DS00
PD61P34B
2.1 Program Memory (One-time PROM) ... 1002 steps x 10 bits
This one-time PROM is configured with 10 bits per step and is addressed by the program counter. The program memory stores programs and table data. The 22 steps from addresses 3EAH through 3FFH constitute a test program area and must not be used. Figure 2-1. Program Memory Map
10 bits 000H
3E9H 3EAH 3FFH
Test program areaNote
Note Even if execution jumps to the test program area by mistake, it returns to address 000H.
Data Sheet U13595EJ2V0DS00
11
PD61P34B
3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)
The program memory of the PD61P34B is a one-time PROM of 1002 x 10 bits. To write or verify this one-time PROM, the pins shown in Table 3-1 are used. Note that no address input pin is used. Instead, the address is updated by using the clock input from the CLK pin. Table 3-1. Pins Used to Write/Verify Program Memory
Pin Name VPP VDD CLK MD0-MD3 D0-D7 XIN, XOUT Function Supplies voltage when writing/verifying program memory. Apply +12.5 V to this pin. Power supply. Supply +6 V to this pin when writing/verifying program memory. Inputs clock to update address when writing/verifying program memory. By inputting pulse four times to CLK pin, address of program memory is updated. Input to select operation mode when writing/verifying program memory. Inputs/outputs 8-bit data when writing/verifying program memory. Clock necessary for writing program memory. Connect 500-kHz ceramic resonator to this pin.
3.1 Operating Mode When Writing/Verifying Program Memory
The PD61P34B is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the PD61P34B has been in the reset status (VDD = 5 V, VPP = 0 V) for a specific time. In this mode, the operating modes shown in Table 3-2 can be set by setting the MD0 through MD3 pins. Connect all the pins other than those shown in Table 3-1 to GND via pull-down resistor. Table 3-2. Setting Operation Mode
Setting of Operating Mode VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L x MD2 H H H H MD3 L H H H Clear program address to 0 Write mode Verify mode Program inhibit mode Operation Mode
x: don't care (L or H)
12
Data Sheet U13595EJ2V0DS00
PD61P34B
3.2 Program Memory Writing Procedure
The program memory is written at high speed in the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the VDD pin. Keep the VPP pin low. Supply 5 V to the VPP pin after waiting for 10 s. Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes. Set the program memory address 0 clear mode by using the mode setting pins. Supply 6 V to VDD and 12.5 V to VPP. Set the program inhibit mode. Write data to the program memory in the 1-ms write mode. Set the program inhibit mode. steps (8) through (10). (11) Additional writing of (number of times of writing in (8) through (10): X) x 1 ms. (12) Set the program inhibit mode. (13) Input a pulse to the CLK pin four times to update the program memory address (+1). (14) Repeat steps (8) through (13) up to the last address. (15) Set the 0 clear mode of the program memory address. (16) Change the voltages on the VDD and VPP pins to 5 V. (17) Turn off power. The following figure illustrates steps (2) through (13) above.
Repeated X time Write Verify Additional write Address increment
(10) Set the verify mode. If the data have been written to the program memory, proceed to (11). If not, repeat
Oscillation stabilization wait time
Reset VPP VPP VDD GND VDD VDD+1 VDD GND CLK
D0-D7
Hi-Z
Data input
Hi-Z
Data output
Hi-Z
Data input
Hi-Z
MD0
MD1
MD2
MD3
Data Sheet U13595EJ2V0DS00
13
PD61P34B
3.3 Program Memory Reading Procedure
(1) (2) (3) (4) (5) (6) (7) (8) (9) Pull down the pins not used to GND via resistor. Keep the CLK pin low. Supply 5 V to the VDD pin. Keep the VPP pin low. Supply 5 V to the VPP pin after waiting for 10 s. Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes. Set the program memory address 0 clear mode by using the mode setting pins. Supply 6 V to VDD and 12.5 V to VPP. Set the program inhibit mode. Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to the CLK pin four times. Set the program inhibit mode. (10) Set the program memory address 0 clear mode. (11) Change the voltage on the VDD and VPP pins to 5 V. (12) Turn off power. The following figure illustrates steps (2) through (10) above.
Oscillation stabilization wait time
Reset VPP VPP VDD GND VDD+1 VDD GND CLK
VDD
D0-D7
Hi-Z
Data output
Data output
Hi-Z
MD0
MD1
"L"
MD2
MD3
14
Data Sheet U13595EJ2V0DS00
PD61P34B
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25 C)
Parameter Power supply voltage Symbol VDD VPP Input voltage Output voltage High-level output current VI VO IOH
Note
Test Conditions
Rating -0.3 to +7.0 -0.3 to +13.5
Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
KI/O, KI, S0, S1, RESET
-0.3 to VDD + 0.3 -0.3 to VDD + 0.3
REM
Peak value rms
-30 -20 -7.5 -5 -13.5 -9 -18 -12 7.5 5 7.5 5 -40 to +85 -65 to +150
LED
Peak value rms
One KI/O pin
Peak value rms
Total of LED and KI/O pins IOL Note
Peak value rms
Low-level output current
REM
Peak value rms
LED
Peak value rms
Operating ambient temperature Storage temperature
TA Tstg
Note Work out the rms with: [rms] = [Peak value] x Duty. Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momentarily. In other words, an absolute maxumum rating is a value at which the possibility of psysical damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the these ratings are not exceeded during use of the product. Recommended Power Supply Voltage Range (TA = -40 to +85 C)
Parameter Power supply voltage Symbol VDD Test Conditions fX = 300 to 500 kHz fX = 500 kHz to 1 MHzNote MIN. 2.2 2.2 TYP. 3.0 3.0 MAX. 3.6 3.6 Unit V V
Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.2 V.
Data Sheet U13595EJ2V0DS00
15
PD61P34B
DC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 3.6 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 Low-level input voltage VIL1 VIL2 VIL3 High-level input leakage current ILH2 Low-level input leakage current IUL1 IUL2 IUL3 High-level output voltage Low-level output voltage VOH1 VOL1 VOL2 High-level output current IOH1 IOH2 Low-level output current IOL1 ILH1 RESET KI/O KI, S0, S1 RESET KI/O KI, S0, S1 KI VI = VDD, pull-down resistor not incorporated S0, S1 VI = VDD, pull-down resistor not incorporated KI KI/O S0, S1 VI = 0 V VI = 0 V VI = 0 V IOH = -0.3 mA IOL = 0.3 mA IOL = 15 A VDD = 3.0 V, VOH = 1.0 V VDD = 3.0 V, VOH = 2.2 V VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOL = 2.2 V Built-in pull-up resistor Built-in pull-down resistor R1 R2 R3 R4 Data hold power supply voltage Supply currentNote VDDOR IDD1 RESET RESET KI, S0, S1 KI/O In STOP mode Operating mode IDD2 HALT mode fX = 1.0 MHz, VDD = 3 V 10 % fX = 455 kHz, VDD = 3 V 10 % fX = 1.0 MHz, VDD = 3 V 10 % fX = 455 kHz, VDD = 3 V 10 % IDD3 STOP mode VDD = 3 V 10 % VDD = 3 V 10 %, TA = 25 C -5 -2.5 30 100 25 2.5 75 130 1.2 0.6 0.5 0.5 0.4 1.0 1.0 -9 -5 70 220 50 5 150 250 100 15 300 500 3.6 1.2 1.0 1.0 0.8 8.0 2.0 0.8 VDD 0.3 0.4 Test Conditions MIN. 0.8 VDD 0.65 VDD 0.65 VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2 VDD 0.3 VDD 0.15 VDD 3 3 -3 -3 -3 Unit V V V V V V
A A A A A
V V V mA mA
REM, LED, KI/O REM, LED KI/O REM KI/O KI/O
A A
k k k k V mA mA mA mA
A A
Note The POC circuit current and the current flowing in the built-in pull-up resistor are not included.
16
Data Sheet U13595EJ2V0DS00
PD61P34B
AC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 3.6 V)
Parameter Symbol Test Conditions MIN. 15.9 Note 1 KI, S0, S1 high-level width tH When releasing standby mode at HALT mode at STOP mode RESET low-level width tRSL 7.9 10 10 Note 2 10 TYP. MAX. 27 27 Unit
Instruction execution time tCY
s s s s s s
Notes 1. When using at fX = 500 kHz or higher, it is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.2 V. 2. 10 + 260/fX + oscillation growth time Remark tCY = 8/fX (fX: System clock oscillator frequency) POC CircuitNote 1 (TA = -20 to +70 C)
Parameter POC-detected voltageNote 2 Symbol VPOC IPOC Test Conditions MIN. 1.8 TYP. 2.0 1.2 MAX. 2.2 1.5 Unit V
POC circuit current
A
Notes 1. Operates effectively under the conditions of fX = 300 to 500 kHz. 2. Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset is canceled. From the time of VPOC VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period of VPOC VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 2.2 to 3.6 V)
Parameter Oscillator frequency (ceramic resonator) Symbol fX Note Test Conditions MIN. 300 300 TYP. 455 455 MAX. 500 1000 Unit kHz kHz
Note When using at fX = 500 kHz or higher, it is necessary to design the application circuit so that the RESET pin goes low when the supply voltage is less than 2.2 V. An external circuit example
XIN
XOUT Rd
C1
C2
Data Sheet U13595EJ2V0DS00
17
PD61P34B
PROM Programming Mode DC Programming Characteristics (TA = 25 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V)
Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Test Conditions Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 MIN. 0.7 VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Keep VPP to within +13.5 V including overshoot. 2. Apply VDD before VPP and turns it off after VPP.
18
Data Sheet U13595EJ2V0DS00
PD61P34B
AC Programming Characteristics (TA = 25 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V)
Parameter Address setup timeNote 2 (vs. MD0) MD1 setup time (vs. MD0) Data setup time (vs. MD0) Address hold timeNote 2 (vs. MD0) Symbol tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR tOAD tHAD tM3HR tDFR tRES tWAIT Note1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - - - -
When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read
Test Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
Data hold time (vs. MD0) MD0 data output float delay time VPP setup time (vs. MD3) VDD setup time (vs. MD3) Initial program pulse width Additional program pulse width MD0 setup time (vs. MD1) MD0 data output delay time MD1 hold time (vs. MD0) MD1 recovery time (vs. MD0) Program counter reset time CLK input high-, low-level width CLK input frequency Initial mode set time MD3 setup time (vs. MD1) MD3 hold time (vs. MD1) MD3 setup time (vs. MD0) AddressNote 2 data output delay time AddressNote 2 data output hold time MD3 hold time (vs. MD0) MD3 data output float delay time Reset setup time Oscillation stabilization wait timeNote 3
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H+tM1R 50 s 2 2 10 0.125
s s s s s
8 2 2 2 2 2 0 2 2 10 2 130
MHz
s s s s s
ns
s s s
ms
Notes 1. Equivalent symbol of the corresponding PD27C256A (The PD27C256A is a maintenance product.) 2. The internal address signal is incremented at the falling edge of the third clock of CLK. 3. Connect a 500-kHz ceramic resonator between the XIN and XOUT pins.
Data Sheet U13595EJ2V0DS00
19
PD61P34B
Program Memory Write Timing
tWAIT VPP VDD GND tRES tVPS
VPP
tVDS tXH
VDD+1 VDD VDD GND CLK
Hi-Z Hi-Z Hi-Z
D0-D7
tXL
Data input
Data input
Data output
Hi-Z
Data input
Hi-Z
tt MD0
tDS
tDH
tDV
tDF
tDS
tDH tAH
tAS
tPW MD1 tPCR MD2 tM3S MD3 tM1S tM1H
tM1R
tMOS
tOPW
tM3H
Program Memory Read Timing
tWAIT tRES tVPS VPP VPP VDD GND VDD+1 VDD VDD GND CLK tXL D0-D7 tI MD0
Hi-Z Data output
tVDS tXH
tDAD tMAD
Hi-Z Data output
tDV
tDFR tM3HR
MD1 tPCR MD2 tM3SR MD3
"L"
20
Data Sheet U13595EJ2V0DS00
PD61P34B
5. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (fX = 455 kHz)
(TA = 25 C ) 1 0.9 Power supply current IDD [mA] 0.8 0.7 OPERATING mode 0.6 0.5 HALT mode 0.4 0.3 0.2 0.1 0 1 2 2.2 3 3.6 4 Power supply voltage VDD [V] Power supply current IDD [mA] 1 0.9 0.8 OPERATING mode 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 2.2 3 3.6 4 Power supply voltage VDD [V] HALT mode
IDD vs VDD (fX = 1 MHz)
(TA = 25 C)
IOL vs VOL (REM, LED)
(TA = 25 C, VDD = 3.0 V) 10 9 8 7 6 5 4 3 2 1 0 0.6 1.2 1.8 2.4 3 High-level output current IOH [mA] Low-level output current IOL [mA] -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 VDD
IOH vs VOH (REM)
(TA = 25 C , VDD = 3.0 V)
VDD - 0.6 VDD - 1.2 VDD - 1.8 VDD - 2.4 VDD - 3 High-level output voltage VOH [V]
Low-level output voltage VOL [V]
IOH vs VOH (LED)
(TA = 25 C , VDD = 3.0 V) -10 -9 High-level output current IOH [mA] -8 -7 -6 -5 -4 -3 -2 -1 0 VDD VDD - 0.6 VDD - 1.2 VDD - 1.8 VDD - 2.4 VDD - 3 High-level output voltage VOH [V]
Data Sheet U13595EJ2V0DS00
21
PD61P34B
IOL vs VOL (KI/O)
(TA = 25 C, VDD = 3.0 V) -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 VDD
IOH vs VOH (KI/O)
(TA = 25 C, VDD = 3.0 V)
280 240 200 160 120 80 40 0 0.6 1.2 1.8 2.4 3
High-level output current IOH [mA]
320
Low-level output current IOL [ A]
VDD - 0.6 VDD - 1.2 VDD - 1.8 VDD - 2.4 VDD - 3 High-level output voltage VOH [V]
Low-level output voltage VOL [V]
22
Data Sheet U13595EJ2V0DS00
PD61P34B
6. APPLIED CIRCUIT EXAMPLE
Example of Application to System * Remote-control transmitter (40 keys; mode selection switch accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND RESET
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 5 = 40 keys Mode selection switch
* Remote-control transmitter (48 keys accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND RESET
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 6 = 48 keys
Remark When the POC circuit is used effectively, it is not necessary to connect the capacitor enclosed in the dotted lines.
Data Sheet U13595EJ2V0DS00
23
PD61P34B
7. PACKAGE DRAWINGS
20 PIN PLASTIC SOP (300 mil)
20 11 detail of lead end
P
1 A
10
H G I J
L C D E F
NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P MILLIMETERS 12.70.3 0.78 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.10.1 1.8 MAX. 1.550.05 7.70.3 5.60.2 1.1 0.22 +0.08 -0.07 0.60.2 0.12 0.10 3 +7 -3 INCHES 0.5000.012 0.031 MAX. 0.050 (T.P.) 0.017 +0.003 -0.004 0.0040.004 0.071 MAX. 0.0610.002 0.3030.012 0.220 +0.009 -0.008 0.043 0.009 +0.003 -0.004 0.024 +0.008 -0.009 0.005 0.004 3 +7 -3 P20GM-50-300B, C-5
B N
K
M
M
24
Data Sheet U13595EJ2V0DS00
PD61P34B
20 PIN PLASTIC SSOP (300 mil)
20 11
detail of lead end F G T
P E 1 A H I S 10
L U
J
N C D
NOTE
S K
M
M
B
ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.650.15 0.475 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S20MC-65-5A4-1
Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.
Data Sheet U13595EJ2V0DS00
25
PD61P34B
8. RECOMMENDED SOLDERING CONDITIONS
Carry out the soldered packaging of this product under the following recommended conditions. For details of the soldering conditions, refer to information material Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than the recommended conditions, please consult one of our NEC sales representatives. Table 8-1. Soldering Conditions for Surface-Mount Type (1) PD61P34BGS: 20-pin plastic SOP (300 mil)
Recommended Condition Symbol IR35-00-2 VP15-00-2
Soldering Method Infrared reflow VPS
Soldering Condition Package peak temperature: 235 C, Time: 30 secs. max. (210 C min.), Number of times: Twice max. Package peak temperature: 215 C, Time: 40 secs. max. (200 C min.), Number of times: Twice max. Solder bath temperature: 260 C max., Time: 10 secs. max., Number of times: once, Preheating temperature: 120 C max. (package surface temperature.) Pin temperature: 300 C or less ; time: 3 secs or less (for each side of the device)
Wave soldering
WS60-00-1
Partial heating
--
Caution Do not use two or more soldering methods in combination (except partial heating). (2) PD61P34BMC-5A4: 20-pin plastic SSOP (300 mil)
Recommended Condition Symbol IR35-00-3 VP15-00-3
Soldering Method Infrared reflow VPS
Soldering Condition Package peak temperature: 235 C, Time: 30 secs. max. (210 C min.), Number of times: Three times max. Package peak temperature: 215 C, Time: 40 secs. max. (200 C min.), Number of times: Three times max. Solder bath temperature: 260 C max., Time: 10 secs. max., Number of times: once, Preheating temperature: 120 C max. (package surface temperature.) Pin temperature: 300 C or less ; time: 3 secs or less (for each side of the device)
Wave soldering
WS60-00-1
Partial heating
--
Caution Do not use two or more soldering methods in combination (except partial heating).
26
Data Sheet U13595EJ2V0DS00
PD61P34B
APPENDIX A. DEVELOPMENT TOOLS
A PROM programmer, program adapter, and an emulator are provided for the PD61P34B. Hardware * PROM programmer (AF-9704Note, AF-9705 Note, AF-9706Note) These PROM programmers support the PD61P34B. By connecting a program adapter to this PROM programmer, the PD61P34B can be programmed. Note These are products of Ando Electric. For details, consult Ando Electric (03-3733-1163). * Program adapter (PA-61P34, PA-61P34BMC) These are used to program the PD61P34B in combination with AF-9704, AF-9705, or AF-9706. The usable package differs depending on the program adapter. * PA-61P34 : PD61P34BGS * PA-61P34BMC: PD61P34BGS, PD61P34BMC-5A4 * Emulator (EB-6133Note) It is used to emulate the PD61P34B. Note This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Software * Assembler (AS6133) * This is a development tool for remote control transmitter software. Part Number List of AS6133
Host Machine PC-9800 series (CPU: 80386 or more) IBM PC/ATTM compatible MS-DOSTM OS (Ver. 5.0 to Ver. 6.2) Supply Medium 3.5-inch 2HD 3.5-inch 2HC Part Number
S5A13AS6133 S7B13AS6133
MS-DOS (Ver. 6.0 to Ver. 6.22) PC DOSTM (Ver. 6.1 to Ver. 6.3)
Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software.
Data Sheet U13595EJ2V0DS00
27
PD61P34B
APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (in the case of NEC transmission format in command one-shot transmission mode)
Caution When using the NEC transmission format, please apply for a custom code at NEC. (1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.)
REM output 58.5 to 76.5 ms <1> 108 ms
<2> 108 ms
Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1>
<3> REM output 9 ms 4.5 ms Custom code 8 bits Custom code' 8 bits Data code 8 bits 27 ms Data code 8 bits Stop Bit 1 bit
13.5 ms Leader code
18 to 36 ms 58.5 to 76.5 ms
(3) Enlarged waveform of <3>
REM output 9 ms 13.5 ms 4.5 ms 0.56 ms 1.125 ms 2.25 ms 0 1
1
0
0
(4) Enlarged waveform of <2>
REM output 9 ms 11.25 ms Leader code 2.25 ms 0.56 ms Stop Bit
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Data Sheet U13595EJ2V0DS00
PD61P34B
(5) Carrier waveform (Enlarged waveform of each code's high period)
REM output 8.77 s 26.3 s 9 ms or 0.56 ms Carrier frequency : 38 kHz
(6) Bit array of each code
C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
= = = = = = = =
C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or Co C1 C2 C3 C4 C5 C6 C7
Leader code
Custom code
Custom code'
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the 16-bit custom codes (Custom Code, Custom Code') and the 16-bit data codes (Data Code, Data Code) but also check to make sure that no signals are present.
Data Sheet U13595EJ2V0DS00
29
PD61P34B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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Data Sheet U13595EJ2V0DS00
PD61P34B
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U13595EJ2V0DS00
31
PD61P34B
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT and PC DOS are trademarks of IBM Corp.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8
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